This invention relates to methods for implementing circuit designs in physical circuits, and more particularly to comparing two circuit designs so that as much as possible of work that has been done with regard to implementing a first circuit design can be reused in implementing the second circuit design.
The task of implementing a complex electrical circuit design in physical circuitry can be a formidable one. For example, there are various types of general purpose, programmable circuit devices that can be used to implement a wide variety of circuit designs. Illustrative of these types of devices are programmable logic arrays ("PLAs"), field programmable gate arrays ("FPGAs"), and other similar programmable integrated circuit devices. (See Cliff et al. U.S. Pat. No. 5,260,611 and commonly assigned, co-pending U.S. patent application Ser. No. 08/442,795, filed May 17, 1995, for examples of PLA devices. These documents are hereby incorporated by reference herein.) Typically, in the use of these kinds of devices the user devises a logic circuit design for performing desired logic functions. This circuit-design phase may be computer assisted (e.g., using a system such as the MAX+PLUS II Programmable Logic Development System, which is commercially available from Altera Corporation of San Jose, Calif., and which is described, for example, in the Altera publications "MAX+PLUS II Getting Started", Version 5.0, July 1994, and "MAX+PLUS II AHDL", Version 5.0, July 1994, both of which are hereby incorporated by reference herein.) Additional modules of this computer software are then frequently used to translate the user's circuit design into a set of components and inter-component connections that can be implemented in the physical circuitry of the device to be used to implement the design. For example, this process may involve breaking the user's circuit design into a plurality of components, each of which is implementable in a respective one of the physical circuit components of the intended device. (In this case a physical circuit component may be a logic gate, a logic module (e.g., circuitry capable of forming any logical combination of several inputs), or a logic array block (e.g., several interconnected logic modules).) In addition, all necessary connections between the circuit design components are identified for implementation in the interconnection resources of the intended device. Such a decomposition of the user's logic design may be embodied in a structured list of all required logic components and their interconnections. A list of this type is sometimes referred to as a "netlist," and that term is therefore employed herein with that meaning.
After a netlist has been generated, considerable further work must often be done--again by other portions of the above-mentioned software--to decide how the netlist circuitry will actually be implemented in physical circuitry. This process may involve such steps as synthesis (i.e., determining how a unit of available physical circuitry will be programmed to implement each design component), partitioning (i.e., grouping the design components into clusters that fit into available physical circuit clusters without excessive interconnections being required between the clusters), and placing and routing (i.e., assigning each design circuit cluster to a particular respective physical circuit cluster so that required connections can be made between the clusters without any required connection being blocked by other required connections).
Because so much computational effort often goes into implementing a netlist, it would be desirable to be able to reuse as much of that work as possible when there is a change in the circuit design.
In view of the foregoing, it is an object of this invention to provide methods for implementing circuit designs in physical circuitry which reduce the need to re-perform such steps as circuit synthesis, circuit partitioning, and circuit placement and routing when the circuit design changes.
It is a more particular object of this invention to provide methods for comparing netlists of circuit designs before and after design changes in such a way that unchanged portions of the design are identified so that the work of implementing those portions of the circuit can be reused in implementing the changed design.